In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on\nnanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a\nwidely used consumer appliance, it is aimed to be such designed to consume power as low as possible.\nHence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the\nbits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to\nestablish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V,\nresulting to an ultralow power of 52.9 �µW. Many other powerful ideas are then deliberately combined to\nmaintain both high speed and very low glitches required for HDTV application despite those ultralow currents\nand power. The result is a speed of 100 MS/s, an ultralow glitch of ?10.91 fAs, |INL| = 0.988 LSB, |DNL|\n= 0.99 LSB, and a spurious-free dynamic range of ?73 dB. These results caused the proposed DAC to execute\na distinguished overall performance (defined as figure of merit) greatly better than some other advanced\nones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-�µm complementary\nmetal-oxide semiconductor technology have been used to validate the proposed circuit. Performance\nevaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature\nvariations proved both its well mismatch insensitivity and thermal stability.
Loading....